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NCP5680
TOUT[7..0] Time Out register $14
B7
B6
B5
B4
B3
B2
B1
B0
ms
RESET
256
0
128
0
64
0
32
1
16
1
8
0
4
0
2
1
The minimum time out is preset at 50 ms.
NOTE:
Tolerance of the Fpwr Clock parameter applies to the timing parameters.
“The Time Out function can be de-activated to generate the infinite operation requested by the Video mode. To achieve such
a function, the here below logic conditions must be met:
? ICHG register: bits B7 = B6 = 1
? CONFIG1 register: bit B3 = 1 (external trigger flash only)
? FILED1 and FILED2 must be lower or equal to 500 mA each
The Time out is maintained is any of the three conditions is not fulfilled.”
DC/DC Operation
The converter is based on a charge pump technique to generate a constant DC voltage capable to either re ? charge the
external Super Cap, or to drive the LED in the torch mode. The system regulates the current flowing into the LED by means
of an internal current mirror associated with the external shunt resistor and the external power NMOS. The output voltage
is adjusted and regulated in the range 4.5 V to 5.5 V across the external Super Cap reservoir, the NMOS device being used
as a current controlled source to drive the LED. When the DC/DC is not active, the voltage across the external reservoir
capacitor is either zero or equal to the voltage present at the Vbat pin, depending upon the operation defined by the SACT
bit in the CONFIG1 register.
The output current is setup by the external reference
resistor connected between Vout and the LED. With a
100 mV drop across the shunt resistor, the forward current
into the LED being: ILed = 0.10/R. The shunt resistor must
be sized to sustain the amount of current flowing during the
operation.
The Vout voltage is continuously monitored and the
charge pump stops when the voltage is above the maximum
programmed value. The converter resumes to normal
operation when the voltage drops below the programmed
value (there is no fault latched since the converter operates
in the hysteretic regulation mode). Consequently, the chip
can operate under no load conditions during any test
procedures with no risk in term of OVP situation.
However, when the check routine is activated, the
voltage present at the drain of the external NMOS is
Figure 4. Typical Pre Charge Sequence
Table 2. LED Drive Overload Detection Conditions
monitored to detect fault condition that might develop in
the power flash structure according to Table 2.
Vds
0V
0V
0 V < Vds < Vout
= Vout
> 2.0 V
NCP5680 status
Standby
Pulsed Flash
Standby
Standby
Pulsed Flash
Fault
LED open or Cathode to ground shorted
LED open or Cathode to ground shorted
Normal operation, no fault
Anode to Cathode LED shorted
Anode to Cathode LED shorted, Charge pump de ? activated, flash de ? activated
When the check routine is activated, the result is stored
into the STATUS register and can be read back by the I2C
port.
On the other hand, the external SuperCAP re ? charge
current can be programmed, through the I2C port, to better
handle the total energy demand. The three bits present in
the ICHG register makes possible the adjustment of the
re ? charge current from 100 mA to 500 mA, keeping in
mind that the charge pump is designed to supply up to
500 mA maximum.
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